1. Technical Field
This disclosure relates to failure analysis and more particularly, to a failure analysis method which preferably employs xenon-difluoride gas for preparing semiconductor chips for the failure analysis.
2. Description of the Related Art
Dielectric integrity is always a concern in integrated circuit fabrication. Failed semiconductor chips are typically analyzed to discover causes of the failure or failure modes. For example, holes formed in thin oxides can be prepared and highlighted by using a two-step process in which a semiconductor chip sample is, in a first step, delayered top-down or cross-sectioned close to a target area to be observed. The target area is typically a location believed to be the cause of the failure. In a second step, the delayered top-down or cross-sectioned target area is etched using a selective silicon etch. This is followed by a scanning electron microscopy (SEM) inspection.
There are several age-old methods for analyzing dielectric integrity. Electrical methods include breakdown voltage analysis, charge to breakdown analysis, capacitance analysis, and photoemission. These electrical techniques are almost always coupled with physical analysis for confirmation and further learning. The physical analysis typically involves wet chemistry to highlight defects either in the dielectric or the underlying Si. KOH is commonly used to highlight oxide pinholes because it is highly selective, etching Si about 200 times more rapidly than SiO.sub.2. Silicon decoration etchants, such as a Wright etch, dash etch, or Secco etch, are often employed to highlight pinhole damage to the Si substrate, indirectly showing oxide integrity problems.
All known methods for preparing and etching samples are ex-situ techniques. That is these techniques are carried out outside a focused ion beam (FIB) or SEM chamber. In other words, samples are removed from the FIB or SEM chamber before target areas can be exposed and/or etched for inspection inside the chamber(s). For etching, a selective Si-etch (e.g. KOH) is used. For delayering or cross-sectioning a sample, chemical or physical delayering methods (e.g. reactive ion etch (RIE), selective chemical etching, face lapping, etc.) or a combination of both are applied. As with all ex-situ methods, these techniques are strongly dependent on a precise control of every single step involved to assure an accurate result (e.g. temperature and time control during KOH etching). The process is time-consuming and requires skilled personnel to guarantee reliable results. Deviations from the original process (e.g. different layout, layer thicknesses) can enforce a readjustment of the whole process. Furthermore, the monitoring of the progress of the delayering/cross-sectioning or etching processes involves a frequent and time-consuming sample transfer into a (U)HV-chamber of an SEM (at least for modern Ultra Large Scale Integration (ULSI) semiconductor technology). Additionally, a subsequent KOH etch may be affected by Gallium-poisoning of the Si in the sample and by raster burn of the electron beam. These prior art methods are both difficult to control and time-consuming.
Therefore, a need exists for a fast, selective, site-specific method to find pinholes in dielectrics, other failed components or defects in semiconductor devices.